1. Field of the Invention
This invention relates to a data storage device and, more particularly, to a storage device incorporating a data common memory and an attribute memory. This invention also relates to a method of accessing such a data storage device.
2. Description of the Related Art
FIG. 5 shows a conventional portable semiconductor data storage device. The data storage device has a common memory 1 formed of a volatile memory, such as a static random access memory (SRAM), and an attribute memory 2 formed of a non-volatile memory, such as an electrically erasable/programmable random access memory (EEPROM). The common memory 1 stores data processed in the memory system, and the attribute memory 2 stores to store attribute data of the data storage device. When the voltage of a power input line 14 becomes equal to or higher than a prescribed voltage after this storage device has been connected to a terminal unit (not shown) and supplied with power from the terminal unit through the power input line 14, a power supply control circuit 5 connects the power input line 14 to an internal power supply line 15 and sends a memory backup protection signal at high level to a first chip selection signal input terminal S1 of the common memory 1 through a signal line 16.
In this state, the terminal unit can access the common memory 1 or the attribute memory 2. To access the attribute memory 2, both a memory chip enable signal on a signal line 11 and a register signal on a signal line 12 are set to low level. Then, a chip selection signal at low level is supplied to a chip selection signal input terminal S1 of the attribute memory 2 through a gate circuit 7 for selecting the attribute memory 2, while a chip selection signal at high level is supplied to a second chip selection signal input terminal S2 of the common memory 1 through a gate circuit 6. The attribute memory 2 is thereby selected and the terminal unit is enabled to perform writing/reading in the attribute memory 2 through an address bus 8, a write enable signal line 9, an output enable signal line 10, a data bus 13, an input buffer circuit 3 and an input/output buffer circuit 4.
To access the common memory 1, the memory chip enable signal on the signal line 11 and the register signal on the signal line 12 are set to low level and high level, respectively. Then, the chip selection signal at low level is supplied to the second chip selection signal input terminal S2 of the common memory 1 through the gate circuit 6 for selecting the common memory, while the chip selection signal at high level is supplied to the chip selection signal input terminal S1 of the attribute memory 2 through the gate circuit 7. The common memory 1 is thereby selected and the terminal unit is enabled to perform writing/reading in the common memory 1 through the address bus 8, the write enable signal line 9, the output enable signal line 10, the data bus S3, the input buffer circuit 3 and the input/output buffer circuit 4.
The operation when in a case where the power supply from the terminal unit is stopped or the voltage of the power input line 14 is lower than the prescribed level will be described. In such a case, the power supply control circuit 5 disconnects the power input line 14 and the internal power supply line 15 and supplies the memory backup protection signal at low level to the first chip selection signal input terminal S1 of the common memory 1 through the signal line 16 to back up the common memory 1. At this time, electric power is supplied to the common memory 1 from a primary battery 26 incorporated in the data storage device through an excess current protection resistor 25, a reverse charge prevention diode 24 and the internal power supply line 15, whereby data stored in the common memory 1 is maintained. Since the attribute memory 2 is a non-volatile memory, data stored therein is not changed.
An output enable signal on the signal line 10 is input through the input buffer circuit 3 and is thereafter supplied as a memory output enable signal to the attribute memory 2 through a signal line 19. Simultaneously, this signal is supplied to a DIR terminal of the input/output buffer circuit 4 to effect direction control of the input/output buffer circuit 4. Also, the memory chip enable signal on the signal line 11 is supplied to a G terminal of the input/output buffer circuit 4, and the input/output buffer circuit 4 is set in an enabled state when one of the common memory 1 and the attribute memory 2 is selected, that is, the memory chip enable signal is at low level.
Thus, the data storage device, reading/writing in the common memory 1 or the attribute memory 2 can be performed freely by controlling the memory chip enable signal on the signal line 11 and the register signal on the signal line 12, if the voltage of the power input line 14 is equal to or higher than the prescribed level. There is therefore a risk that irreplaceable or valuable stored data may be altered, copied or forged.